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| author | Angel Pons <th3fanbus@gmail.com> | 2020-08-03 16:15:16 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 21:35:26 +0000 |
| commit | 4a2f08c846bd835808a23d1cb699899aaf31cf94 (patch) | |
| tree | 8d0ebaa2a2e3929defb9773886b36083c6976d92 /src/northbridge/intel/i945/i945.h | |
| parent | cff4d1649f8a2b890521b53d8b7a6cb5c210d50e (diff) | |
| download | coreboot-4a2f08c846bd835808a23d1cb699899aaf31cf94.tar.gz coreboot-4a2f08c846bd835808a23d1cb699899aaf31cf94.tar.bz2 coreboot-4a2f08c846bd835808a23d1cb699899aaf31cf94.zip | |
nb/intel/i945: Deduplicate PCIEXBAR decoding
We can use `decode_pcie_bar` instead, if we make it non-static.
Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/i945/i945.h')
| -rw-r--r-- | src/northbridge/intel/i945/i945.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 5275d1bfb74b..64a945dca459 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -364,6 +364,8 @@ void sdram_dump_mchbar_registers(void); u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); +int decode_pcie_bar(u32 *const base, u32 *const len); + /* Romstage mainboard callbacks */ /* Optional: Override the default LPC config. */ void mainboard_lpc_decode(void); |