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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-26 15:10:49 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-28 18:01:15 +0000 |
| commit | 0cc811789cadb4d0ed2364bc5d7fb926b4e79f7e (patch) | |
| tree | 5fa202ecfb72d4050d5c93345b9471d0be8e61f0 /src/northbridge/intel/ironlake | |
| parent | ca8968dbc18553d3bea846d4a2001d7fe179cba0 (diff) | |
| download | coreboot-0cc811789cadb4d0ed2364bc5d7fb926b4e79f7e.tar.gz coreboot-0cc811789cadb4d0ed2364bc5d7fb926b4e79f7e.tar.bz2 coreboot-0cc811789cadb4d0ed2364bc5d7fb926b4e79f7e.zip | |
nb/intel/ironlake/quickpath.c: Correct one value
Commit 56823f53dc6de5a804f7c88b9f24847133ddc876 (nb/intel/ironlake:
Rewrite early QPI init) rewrote this part, but the or-value is missing
one zero. Correct this magic value to align with MRC binaries.
Change-Id: Id7a6766b3f0fe415dea70cbc54afc30f808c8b16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51857
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/ironlake')
| -rw-r--r-- | src/northbridge/intel/ironlake/quickpath.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c index a3455db6d942..82fc1e71a898 100644 --- a/src/northbridge/intel/ironlake/quickpath.c +++ b/src/northbridge/intel/ironlake/quickpath.c @@ -562,7 +562,7 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8) MCHBAR8_OR(0x2ca8, 1); MCHBAR32_AND(0x1890, 0xfdffffff); - MCHBAR32_AND_OR(0x18b4, 0xffff6fff, 0x600); + MCHBAR32_AND_OR(0x18b4, 0xffff6fff, 0x6000); MCHBAR32(0x18a4) = 0x22222222; MCHBAR32(0x18a8) = 0x22222222; MCHBAR32(0x18ac) = 0x22222; |