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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-26 11:01:33 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-06 07:10:40 +0000 |
| commit | b324df6a540d154cc9267c0398654f9142aae052 (patch) | |
| tree | 92d40421578cb31c6581fd005ab093728adeb197 /src/northbridge/intel/ironlake | |
| parent | e22c597bf64413ee4329c8869484d8a1f290f217 (diff) | |
| download | coreboot-b324df6a540d154cc9267c0398654f9142aae052.tar.gz coreboot-b324df6a540d154cc9267c0398654f9142aae052.tar.bz2 coreboot-b324df6a540d154cc9267c0398654f9142aae052.zip | |
arch/x86: Provide readXp/writeXp helpers in arch/mmio.h
These p-suffixed helpers allow dropping pointer casts in call-sites,
which is particularly useful when accessing registers at an offset from
a base address. Move existing helpers in chipset code to arch/mmio.h and
create the rest accordingly.
Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/ironlake')
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 34e56571cad8..af835e285590 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -115,16 +115,6 @@ static u16 read_1d0(u16 addr, int split) return val; } -static void write32p(uintptr_t addr, uint32_t val) -{ - write32((void *)addr, val); -} - -static uint32_t read32p(uintptr_t addr) -{ - return read32((void *)addr); -} - static void sfence(void) { asm volatile ("sfence"); |