nb/intel/pineview: Clean up code and comments

- Reformat some lines of code
- Put names to all MCHBAR registers in a separate file
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
- Align a bunch of things

Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected.

Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 53 insertions, 58 deletions

diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index daf425e4a413..c3969f26a401 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -22,14 +22,10 @@
 #include <option.h>
 #include <types.h>
 
-#define LPC PCI_DEV(0, 0x1f, 0)
-#define D0F0 PCI_DEV(0, 0, 0)
+#define LPC_DEV		PCI_DEV(0, 0x1f, 0)
 
-#define PCI_GCFC	0xf0
-#define MCH_GCFGC	0xc8c
-#define  CRCLK_PINEVIEW	0x02
-#define  CDCLK_PINEVIEW	0x10
-#define MCH_HPLLVCO	0xc38
+#define CRCLK_PINEVIEW	0x02
+#define CDCLK_PINEVIEW	0x10
 
 static void early_graphics_setup(void)
 {
@@ -40,17 +36,18 @@ static void early_graphics_setup(void)
 	const struct device *d0f0 = pcidev_on_root(0, 0);
 	const struct northbridge_intel_pineview_config *config = d0f0->chip_info;
 
-	pci_write_config8(D0F0, DEVEN, BOARD_DEVEN);
+	pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
 
-	/* vram size from CMOS option */
+	/* Fetch VRAM size from CMOS option */
 	if (get_option(&reg8, "gfx_uma_size") != CB_SUCCESS)
 		reg8 = 0;	/* 0 for 8MB */
-	/* make sure no invalid setting is used */
+
+	/* Ensure the setting is valid */
 	if (reg8 > 6)
 		reg8 = 0;
+
 	/* Select 1M GTT */
-	pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, (1 << 8)
-			   | ((reg8 + 3) << 4));
+	pci_write_config16(HOST_BRIDGE, GGC, (1 << 8) | ((reg8 + 3) << 4));
 
 	printk(BIOS_SPEW, "Set GFX clocks...");
 	reg16 = MCHBAR16(MCH_GCFGC);
@@ -61,10 +58,10 @@ static void early_graphics_setup(void)
 	MCHBAR16(MCH_GCFGC) = reg16;
 
 	/* Graphics core */
-	reg8 = MCHBAR8(MCH_HPLLVCO);
+	reg8 = MCHBAR8(HPLLVCO);
 	reg8 &= 0x7;
 
-	reg16 = pci_read_config16(PCI_DEV(0,2,0), 0xcc) & ~0x1ff;
+	reg16 = pci_read_config16(GMCH_IGD, 0xcc) & ~0x1ff;
 
 	if (reg8 == 0x4) {
 		/* 2666MHz */
@@ -77,60 +74,58 @@ static void early_graphics_setup(void)
 		reg16 |= 0xad;
 	}
 
-	pci_write_config16(PCI_DEV(0,2,0), 0xcc, reg16);
+	pci_write_config16(GMCH_IGD, 0xcc, reg16);
 
-	pci_write_config8(PCI_DEV(0,2,0), 0x62,
-		pci_read_config8(PCI_DEV(0,2,0), 0x62) & ~0x3);
-	pci_write_config8(PCI_DEV(0,2,0), 0x62,
-		pci_read_config8(PCI_DEV(0,2,0), 0x62) | 2);
+	pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) & ~0x3);
+	pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) | 2);
 
 	if (config->use_crt) {
 		/* Enable VGA */
-		MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 15);
+		MCHBAR32_OR(DACGIOCTRL1, 1 << 15);
 	} else {
 		/* Disable VGA */
-		MCHBAR32(0xb08) = MCHBAR32(0xb08) & ~(1 << 15);
+		MCHBAR32_AND(DACGIOCTRL1, ~(1 << 15));
 	}
 
 	if (config->use_lvds) {
 		/* Enable LVDS */
-		reg32 = MCHBAR32(0x3004);
+		reg32 = MCHBAR32(LVDSICR2);
 		reg32 &= ~0xf1000000;
-		reg32 |= 0x90000000;
-		MCHBAR32(0x3004) = reg32;
-		MCHBAR32(0x3008) = MCHBAR32(0x3008) | (1 << 9);
+		reg32 |=  0x90000000;
+		MCHBAR32(LVDSICR2) = reg32;
+		MCHBAR32_OR(IOCKTRR1, 1 << 9);
 	} else {
 		/* Disable LVDS */
-		MCHBAR32(0xb08) = MCHBAR32(0xb08) | (3 << 25);
+		MCHBAR32_OR(DACGIOCTRL1, 3 << 25);
 	}
 
-	MCHBAR32(0xff4) = 0x0c6db8b5f;
-	MCHBAR16(0xff8) = 0x24f;
+	MCHBAR32(CICTRL) = 0xc6db8b5f;
+	MCHBAR16(CISDCTRL) = 0x024f;
 
-	MCHBAR32(0xb08) = MCHBAR32(0xb08) & 0xffffff00;
-	MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 5);
+	MCHBAR32_AND(DACGIOCTRL1, 0xffffff00);
+	MCHBAR32_OR(DACGIOCTRL1,  1 << 5);
 
 	/* Legacy backlight control */
-	pci_write_config8(PCI_DEV(0, 2, 0), 0xf4, 0x4c);
+	pci_write_config8(GMCH_IGD, 0xf4, 0x4c);
 }
 
 static void early_misc_setup(void)
 {
-	MCHBAR32(0x30);
-	MCHBAR32(0x30) = 0x21800;
-	DMIBAR32(0x2c) = 0x86000040;
+	MCHBAR32(HIT0);
+	MCHBAR32(HIT0) = 0x00021800;
+	DMIBAR32(HTBONUS1) = 0x86000040;
 	pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200);
 	pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000);
 
 	early_graphics_setup();
 
-	MCHBAR32(0x40);
-	MCHBAR32(0x40) = 0x0;
-	MCHBAR32(0x40);
-	MCHBAR32(0x40) = 0x8;
+	MCHBAR32(HIT4);
+	MCHBAR32(HIT4) = 0;
+	MCHBAR32(HIT4);
+	MCHBAR32(HIT4) = 8;
 
-	pci_write_config8(LPC, 0x8, 0x1d);
-	pci_write_config8(LPC, 0x8, 0x0);
+	pci_write_config8(LPC_DEV, 0x08, 0x1d);
+	pci_write_config8(LPC_DEV, 0x08, 0x00);
 	RCBA32(0x3410) = 0x00020465;
 
 	pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
@@ -138,41 +133,41 @@ static void early_misc_setup(void)
 	pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
 	pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1);
 
-	RCBA32(0x3100) = 0x42210;
+	RCBA32(0x3100) = 0x00042210;
 	RCBA32(0x3108) = 0x10004321;
 	RCBA32(0x310c) = 0x00214321;
-	RCBA32(0x3110) = 0x1;
+	RCBA32(0x3110) = 1;
 	RCBA32(0x3140) = 0x01460132;
 	RCBA32(0x3142) = 0x02370146;
 	RCBA32(0x3144) = 0x32010237;
 	RCBA32(0x3146) = 0x01463201;
-	RCBA32(0x3148) = 0x146;
+	RCBA32(0x3148) = 0x00000146;
 }
 
 static void pineview_setup_bars(void)
 {
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
-	pci_write_config8(D0F0, 0x8, 0x69);
+	pci_write_config8(HOST_BRIDGE, 0x08, 0x69);
 
 	/* Set up all hardcoded northbridge BARs */
-	pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1);
-	pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
-	pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
-	pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1);
+	pci_write_config32(HOST_BRIDGE, EPBAR,   DEFAULT_EPBAR   | 1);
+	pci_write_config32(HOST_BRIDGE, MCHBAR,  DEFAULT_MCHBAR  | 1);
+	pci_write_config32(HOST_BRIDGE, DMIBAR,  DEFAULT_DMIBAR  | 1);
+	pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1);
 
 	/* Set C0000-FFFFF to access RAM on both reads and writes */
-	pci_write_config8(D0F0, PAM0, 0x30);
-	pci_write_config8(D0F0, PAM1, 0x33);
-	pci_write_config8(D0F0, PAM2, 0x33);
-	pci_write_config8(D0F0, PAM3, 0x33);
-	pci_write_config8(D0F0, PAM4, 0x33);
-	pci_write_config8(D0F0, PAM5, 0x33);
-	pci_write_config8(D0F0, PAM6, 0x33);
+	pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
+	pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
+	pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
+	pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
+	pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
+	pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
+	pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
 
 	printk(BIOS_DEBUG, " done.\n");
 }
 
-void pineview_early_initialization(void)
+void pineview_early_init(void)
 {
 	/* Print some chipset specific information */
 	printk(BIOS_DEBUG, "Intel Pineview northbridge\n");
@@ -180,10 +175,10 @@ void pineview_early_initialization(void)
 	/* Setup all BARs required for early PCIe and raminit */
 	pineview_setup_bars();
 
-	/* Miscellaneous set up */
+	/* Miscellaneous setup */
 	early_misc_setup();
 
-	/* Change port80 to LPC */
+	/* Route port80 to LPC */
 	RCBA32(GCS) &= (~0x04);
 	RCBA32(0x2010) |= (1 << 10);
 }