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| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-05 20:21:20 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-10 14:59:46 +0000 |
| commit | 88521881133e62d8f3298388faa718efabc9107a (patch) | |
| tree | b02e605a39741d1416d3ecdd80cdcaa13a774cbc /src/northbridge/intel/sandybridge/early_init.c | |
| parent | d589be3648f3e3c9ef5a0aaac9bfe713c8fef333 (diff) | |
| download | coreboot-88521881133e62d8f3298388faa718efabc9107a.tar.gz coreboot-88521881133e62d8f3298388faa718efabc9107a.tar.bz2 coreboot-88521881133e62d8f3298388faa718efabc9107a.zip | |
nb/intel/sandybridge: Add a bunch of MCHBAR defines
While we are at it, also:
- Rename related variables to match the register names.
- Update some comments to better reflect what some registers are about.
- Add various FIXME comments on registers that seem to be used wrongly.
With BUILD_TIMELESS=1, this commit does not change the coreboot build of:
- Asus P8H61-M PRO with native raminit.
- Gigabyte GA-H61MA-D3V with native raminit.
- Lenovo Thinkpad X230 with native raminit.
- Lenovo Thinkpad X220 with MRC raminit.
Change-Id: I5e5fe56eaa90842dbbdd1bfbbcb7709237b4c486
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/early_init.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 74ae4f5e0865..e966095c84df 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -34,10 +34,10 @@ static void systemagent_vtd_init(void) return; /* setup BARs */ - MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; - MCHBAR32(0x5400) = IOMMU_BASE1 | 1; - MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; - MCHBAR32(0x5410) = IOMMU_BASE2 | 1; + MCHBAR32(VTD1_BASE + 4) = IOMMU_BASE1 >> 32; + MCHBAR32(VTD1_BASE) = IOMMU_BASE1 | 1; + MCHBAR32(VTD2_BASE + 4) = IOMMU_BASE2 >> 32; + MCHBAR32(VTD2_BASE) = IOMMU_BASE2 | 1; /* lock policies */ write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); @@ -126,13 +126,13 @@ static void sandybridge_setup_graphics(void) pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); /* Erratum workarounds */ - reg32 = MCHBAR32(0x5f00); + reg32 = MCHBAR32(SAPMCTL); reg32 |= (1 << 9)|(1 << 10); - MCHBAR32(0x5f00) = reg32; + MCHBAR32(SAPMCTL) = reg32; /* Enable SA Clock Gating */ - reg32 = MCHBAR32(0x5f00); - MCHBAR32(0x5f00) = reg32 | 1; + reg32 = MCHBAR32(SAPMCTL); + MCHBAR32(SAPMCTL) = reg32 | 1; /* GPU RC6 workaround for sighting 366252 */ reg32 = MCHBAR32(0x5d14); @@ -144,9 +144,9 @@ static void sandybridge_setup_graphics(void) reg32 &= ~(1 << 0); MCHBAR32(0x6120) = reg32; - reg32 = MCHBAR32(0x5418); + reg32 = MCHBAR32(PAIR_CTL); reg32 |= (1 << 4) | (1 << 5); - MCHBAR32(0x5418) = reg32; + MCHBAR32(PAIR_CTL) = reg32; } static void start_peg_link_training(void) |