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| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-14 16:36:28 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-09-17 19:35:19 +0000 |
| commit | c8027454baeec2d18c06f537083ca30d3b70c1b0 (patch) | |
| tree | 4f8ded82f2026d414c74092f0c85614d68b64ee8 /src/northbridge/intel/sandybridge/early_init.c | |
| parent | 92717ff3e475546366ac6439a4a0d4852bb2cb60 (diff) | |
| download | coreboot-c8027454baeec2d18c06f537083ca30d3b70c1b0.tar.gz coreboot-c8027454baeec2d18c06f537083ca30d3b70c1b0.tar.bz2 coreboot-c8027454baeec2d18c06f537083ca30d3b70c1b0.zip | |
nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
This allows us to drop some casts to uintptr_t around the tree.
The MCHBAR32 macro still needs a cast to preserve reproducibility.
Only the native raminit path needs the cast, the MRC path does not.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Lenovo ThinkPad X230
- Dell OptiPlex 9010
- Roda RW11 (with MRC raminit)
Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/early_init.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 2ee273c1f414..45b5b8f10a4d 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -52,10 +52,10 @@ static void sandybridge_setup_bars(void) /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); - pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); printk(BIOS_DEBUG, " done\n"); } |