nb,soc/intel: Handle upper RAM boundary

Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

7 files changed, 19 insertions, 46 deletions

diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index faa46e0d8a83..33e101830986 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <assert.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
@@ -11,9 +12,8 @@
 static void mch_domain_read_resources(struct device *dev)
 {
 	int idx;
-	unsigned long tomk, tolmk;
-	unsigned long remapbasek, remaplimitk;
-	const unsigned long basek_4G = 4 * (GiB / KiB);
+	unsigned long tolmk;
+	uint64_t tom, remapbase, remaplimit;
 	struct device *mc_dev;
 
 	pci_domain_read_resources(dev);
@@ -25,28 +25,26 @@ static void mch_domain_read_resources(struct device *dev)
 	tolmk = pci_read_config16(mc_dev, TOLM) >> 11;
 	tolmk <<= 17;
 
-	tomk = pci_read_config8(mc_dev, DRB_ROW_7);
-	tomk <<= 16;
+	tom = pci_read_config8(mc_dev, DRB_ROW_7);
+	tom <<= 26;
 
 	/* Remapped region with a 64 MiB granularity in register
 	   definition. Limit is inclusive, so add one. */
-	remapbasek = pci_read_config16(mc_dev, REMAPBASE) & 0x3ff;
-	remapbasek <<= 16;
+	remapbase = pci_read_config16(mc_dev, REMAPBASE) & 0x3ff;
+	remapbase <<= 26;
 
-	remaplimitk = pci_read_config16(mc_dev, REMAPLIMIT) & 0x3ff;
-	remaplimitk += 1;
-	remaplimitk <<= 16;
+	remaplimit = pci_read_config16(mc_dev, REMAPLIMIT) & 0x3ff;
+	remaplimit += 1;
+	remaplimit <<= 26;
 
 	/* Report the memory regions */
 	idx = 10;
 	ram_resource_kb(dev, idx++, 0, tolmk);
 	mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
 
-	if (tomk > basek_4G)
-		ram_resource_kb(dev, idx++, basek_4G, tomk - basek_4G);
 
-	if (remaplimitk > remapbasek)
-		ram_resource_kb(dev, idx++, remapbasek, remaplimitk - remapbasek);
+	ASSERT(tom == remapbase);
+	upper_ram_end(dev, idx++, remaplimit);
 }
 
 static void mch_domain_set_resources(struct device *dev)
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index d2a8742660f8..f41adf32be18 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -121,12 +121,7 @@ static void mch_domain_read_resources(struct device *dev)
 	 * If >= 4GB installed then memory from TOLUD to 4GB
 	 * is remapped above TOM, TOUUD will account for both
 	 */
-	touud >>= 10; /* Convert to KB */
-	if (touud > 4096 * 1024) {
-		ram_resource_kb(dev, idx++, 4096 * 1024, touud - (4096 * 1024));
-		printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
-		       (touud >> 10) - 4096);
-	}
+	upper_ram_end(dev, idx++, touud);
 
 	printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
 	       "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10);
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index a1bd143dd248..8465561f5de1 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -237,7 +237,7 @@ static void mc_report_map_entries(struct device *dev, uint64_t *values)
 
 static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 {
-	unsigned long base_k, size_k, touud_k, index;
+	unsigned long base_k, size_k, index;
 	struct resource *resource;
 	uint64_t mc_values[NUM_MAP_ENTRIES];
 
@@ -312,11 +312,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 	}
 
 	/* 4GiB -> TOUUD */
-	base_k = 4096 * 1024; /* 4GiB */
-	touud_k = mc_values[TOUUD_REG] >> 10;
-	size_k = touud_k - base_k;
-	if (touud_k > base_k)
-		ram_resource_kb(dev, index++, base_k, size_k);
+	upper_ram_end(dev, index++, mc_values[TOUUD_REG]);
 
 	/* Reserve everything between A segment and 1MB:
 	 *
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index aec0fc0b31f7..af602f1e76df 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -134,8 +134,7 @@ static void mc_read_resources(struct device *dev)
 	mmio_resource_kb(dev, index++, gtt_base / KiB, uma_size_gtt * KiB);
 	mmio_resource_kb(dev, index++, igd_base / KiB, uma_size_igd * KiB);
 
-	if (touud > 4096)
-		ram_resource_kb(dev, index++, (4096 * KiB), ((touud - 4096) * KiB));
+	upper_ram_end(dev, index++, touud * MiB);
 
 	/* This memory is not DMA-capable. */
 	if (touud >= 8192 - 64)
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index bfef56e4c46e..677243232946 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -44,7 +44,6 @@ static void mch_domain_read_resources(struct device *dev)
 	u32 tomk, tolud, tseg_sizek;
 	u32 cbmem_topk, delta_cbmem;
 	u16 index;
-	const u32 top32memk = 4 * (GiB / KiB);
 
 	struct device *mch = pcidev_on_root(0, 0);
 
@@ -108,12 +107,7 @@ static void mch_domain_read_resources(struct device *dev)
 	 * If > 4GB installed then memory from TOLUD to 4GB
 	 * is remapped above TOM, TOUUD will account for both
 	 */
-	touud >>= 10; /* Convert to KB */
-	if (touud > top32memk) {
-		ram_resource_kb(dev, index++, top32memk, touud - top32memk);
-		printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
-			(touud - top32memk) / KiB);
-	}
+	upper_ram_end(dev, index++, touud);
 
 	mmconf_resource(dev, index++);
 
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 51e7847788a1..14fde8b08a60 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -211,11 +211,7 @@ static void mc_read_resources(struct device *dev)
 	 * If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM.
 	 * TOUUD will account for both memory chunks.
 	 */
-	touud >>= 10; /* Convert to KB */
-	if (touud > 4096 * 1024) {
-		ram_resource_kb(dev, index++, 4096 * 1024, touud - (4096 * 1024));
-		printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096);
-	}
+	upper_ram_end(dev, index++, touud);
 
 	add_fixed_resources(dev, index++);
 }
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 035862d49911..015e0ac658fb 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -88,12 +88,7 @@ static void mch_domain_read_resources(struct device *dev)
 	 * If >= 4GB installed then memory from TOLUD to 4GB
 	 * is remapped above TOM, TOUUD will account for both
 	 */
-	touud >>= 10; /* Convert to KB */
-	if (touud > top32memk) {
-		ram_resource_kb(dev, index++, top32memk, touud - top32memk);
-		printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
-		       (touud - top32memk) >> 10);
-	}
+	upper_ram_end(dev, index++, touud);
 
 	printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x size=0x%08x\n",
 	       tomk << 10, uma_sizek << 10);