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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-23 22:51:05 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-26 09:39:04 +0000 |
| commit | 29f391ec8f37e3e7d838bf2d16a4ba190062f1dc (patch) | |
| tree | 059564cac8950cc8cf5953f7f0d3eb9e7971ac47 /src/northbridge/intel | |
| parent | a6c8b4becbd12fe6043557ca1e398c1a7c691007 (diff) | |
| download | coreboot-29f391ec8f37e3e7d838bf2d16a4ba190062f1dc.tar.gz coreboot-29f391ec8f37e3e7d838bf2d16a4ba190062f1dc.tar.bz2 coreboot-29f391ec8f37e3e7d838bf2d16a4ba190062f1dc.zip | |
nb/intel/sandybridge: Add print for PLL_REF100_CFG
This field can take eight different values, depending on the maximum
supported speed for the memory when using the 100 MHz reference clock.
Change-Id: I8f2f04f9444831319d4f7bf0d246d01030b6f864
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_ivy.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 6ff82dd011a0..7d684b2d0e16 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -176,10 +176,12 @@ static void find_cas_tck(ramctr_timing *ctrl) /* 100 MHz reference clock supported */ reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); - ref_100mhz_support = !!((reg32 >> 21) & 0x7); + ref_100mhz_support = (reg32 >> 21) & 0x7; printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" : "no"); + printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); + /* Find CAS latency */ while (1) { /* |