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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-01 22:59:00 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-07 19:25:50 +0000 |
| commit | 30c5e607b3cc49ce8a45e420ffa0e71691b86d7d (patch) | |
| tree | d5dfce36446c2590f580aa8ab36380a446645597 /src/northbridge/intel | |
| parent | 7f8da79777ea6a0db1b3142a22863fdbf1b93e50 (diff) | |
| download | coreboot-30c5e607b3cc49ce8a45e420ffa0e71691b86d7d.tar.gz coreboot-30c5e607b3cc49ce8a45e420ffa0e71691b86d7d.tar.bz2 coreboot-30c5e607b3cc49ce8a45e420ffa0e71691b86d7d.zip | |
nb/intel/haswell: Indent PCI ops with tabs
Change-Id: Ia338ce1a36aa0a14017201c1fc16f84915f55c07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index b19e7bd8b540..7ccfdb13c199 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -547,12 +547,12 @@ static void northbridge_init(struct device *dev) } static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, + .read_resources = mc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, .acpi_fill_ssdt = generate_cpu_entries, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short mc_pci_device_ids[] = { |