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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-02-22 18:35:01 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-24 11:28:06 +0000 |
| commit | 318c3ad6745ade5caa3257df15052131c4a1235b (patch) | |
| tree | 13817bbb3062081eeb25f67c0c084f9c2d7e8ebc /src/northbridge/intel | |
| parent | 522b39e757d53ec0dcf955acab508bd5ae27ed7a (diff) | |
| download | coreboot-318c3ad6745ade5caa3257df15052131c4a1235b.tar.gz coreboot-318c3ad6745ade5caa3257df15052131c4a1235b.tar.bz2 coreboot-318c3ad6745ade5caa3257df15052131c4a1235b.zip | |
nb/intel/haswell/pcie.c: remove disable NOP
The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.
Change-Id: I0443a45522b2267e8e23b28e4e2033f25a7ccbf0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51008
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/pcie.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index d9e77a787acf..a631cc883a71 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -7,12 +7,6 @@ #include <device/pci_ids.h> #include <assert.h> -static void pcie_disable(struct device *dev) -{ - printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev)); - dev->enabled = 0; -} - #if CONFIG(HAVE_ACPI_TABLES) static const char *pcie_acpi_name(const struct device *dev) { @@ -53,7 +47,6 @@ static struct device_operations device_ops = { .enable_resources = pci_bus_enable_resources, .scan_bus = pciexp_scan_bridge, .reset_bus = pci_bus_reset, - .disable = pcie_disable, .init = pci_dev_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) |