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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 15:49:55 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-19 11:19:51 +0000 |
| commit | afc6c0ae12ddd26c05bcc2fa527c7a15d0bca0ad (patch) | |
| tree | db3d89c2712162e04577e2230984778c5ec9f869 /src/northbridge/intel | |
| parent | 260e98fbe7c0aed5cbb1e4360fbaed32711e88d3 (diff) | |
| download | coreboot-afc6c0ae12ddd26c05bcc2fa527c7a15d0bca0ad.tar.gz coreboot-afc6c0ae12ddd26c05bcc2fa527c7a15d0bca0ad.tar.bz2 coreboot-afc6c0ae12ddd26c05bcc2fa527c7a15d0bca0ad.zip | |
mb/google/slippy: Correct memory-down SPD handling
MRC only uses the SPD data for the first index, and ignores the rest.
Moreover, index 1 corresponds to the second DIMM on the first channel,
which does not exist on ULT (only one DIMM per channel is supported).
Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge
code to retrieve the serial number from the correct SPD data block.
Tested on Google Wolf, both channels are still correctly detected.
Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 58ac8a05a37b..c85ca5bb7baf 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -227,6 +227,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data) for (d_num = 0; d_num < NUM_SLOTS; d_num++) { const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; if (dimm_size) { + const int index = ch * NUM_SLOTS + d_num; dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; dimm->ddr_type = MEMORY_TYPE_DDR3; @@ -236,14 +237,14 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = d_num; dimm->bank_locator = ch * 2; memcpy(dimm->serial, - &pei_data->spd_data[dimm_cnt][SPD_DIMM_SERIAL_NUM], + &pei_data->spd_data[index][SPD_DIMM_SERIAL_NUM], SPD_DIMM_SERIAL_LEN); memcpy(dimm->module_part_number, - &pei_data->spd_data[dimm_cnt][SPD_DIMM_PART_NUM], + &pei_data->spd_data[index][SPD_DIMM_PART_NUM], SPD_DIMM_PART_LEN); dimm->mod_id = - (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xff); + (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) | + (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff); dimm->mod_type = SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; |