diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-18 00:29:38 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-01 08:31:44 +0000 |
| commit | d992944d09d8262755d5e993141e744606b679ac (patch) | |
| tree | a5532ce0d7a80efb3d2d44e490e83e9f47df87c0 /src/northbridge/intel | |
| parent | f5e636ccdb6b7f9cbbdf185298b9de11b733b5f2 (diff) | |
| download | coreboot-d992944d09d8262755d5e993141e744606b679ac.tar.gz coreboot-d992944d09d8262755d5e993141e744606b679ac.tar.bz2 coreboot-d992944d09d8262755d5e993141e744606b679ac.zip | |
nb/intel/sandybridge: Clean up `dram_timing` function
Compute timings first, then display them. Drop unneeded comments, too.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45501
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 38 |
1 files changed, 11 insertions, 27 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 698db513bde1..598cfdb1229c 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -503,42 +503,15 @@ static void dram_timing(ramctr_timing *ctrl) else ctrl->CWL = get_CWL(ctrl->tCK); - printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); - - /* Find tRCD */ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); - - /* Find tRAS */ ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); - - /* Find tWR */ ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); - - /* Find tFAW */ ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); - - /* Find tRRD */ ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); - - /* Find tRTP */ ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); - - /* Find tWTR */ ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); - - /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); - printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq); ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq); @@ -548,6 +521,17 @@ static void dram_timing(ramctr_timing *ctrl) ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq); ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq); ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq); + + printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); + printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); + printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); + printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); + printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); + printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); + printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); + printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); + printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); + printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); } static void dram_freq(ramctr_timing *ctrl) |