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| author | Elyes Haouas <ehaouas@noos.fr> | 2022-04-25 16:01:23 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-16 02:40:14 +0000 |
| commit | db735c478e12bebc8a2a4d3559f1ac8f1f15602f (patch) | |
| tree | a66f4721c61b8de0da024cf05fb7ec14301975f8 /src/northbridge/intel | |
| parent | a618e11f1a170db9a2bc2d7556c6cb38db303e3c (diff) | |
| download | coreboot-db735c478e12bebc8a2a4d3559f1ac8f1f15602f.tar.gz coreboot-db735c478e12bebc8a2a4d3559f1ac8f1f15602f.tar.bz2 coreboot-db735c478e12bebc8a2a4d3559f1ac8f1f15602f.zip | |
src: Remove unused <cf9_reset.h>
Found using:
diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<"
Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/ironlake/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index f7177826e544..1e6bf67e3ebe 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -3,7 +3,6 @@ #include <arch/io.h> #include <stdint.h> #include <console/console.h> -#include <cf9_reset.h> #include <device/pci_ops.h> #include <timestamp.h> #include <romstage_handoff.h> |