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| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/northbridge/via/vx900/lpc.c | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
| download | coreboot-bde6d309dfafe58732ec46314a2d4c08974b62d4.tar.gz coreboot-bde6d309dfafe58732ec46314a2d4c08974b62d4.tar.bz2 coreboot-bde6d309dfafe58732ec46314a2d4c08974b62d4.zip | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/via/vx900/lpc.c')
| -rw-r--r-- | src/northbridge/via/vx900/lpc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 3cff6b0bf6eb..61a8a7b96aa7 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -139,10 +139,10 @@ static void vx900_lpc_ioapic_setup(device_t dev) /* The base address of this IOAPIC _must_ be at 0xfec00000. * Don't move this value to a #define, as people might think it's * configurable. It is not. */ - const u32 base = config->base; - if (base != 0xfec00000) { + const void *base = config->base; + if (base != (void *)0xfec00000) { printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at " - "0xfec00000\n but we found it at 0x%.8x\n", base); + "0xfec00000\n but we found it at %p\n", base); return; } |