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| author | Felix Held <felix-coreboot@felixheld.de> | 2024-02-06 16:55:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-23 15:13:37 +0000 |
| commit | 0d19289e840f9c711f50a74437d1b3856222db03 (patch) | |
| tree | ca4e8ce2d51dfa9d10deceb28393a28c061a0952 /src/northbridge | |
| parent | a138cfb422109018ba35c8f5d82621717eaf0611 (diff) | |
| download | coreboot-0d19289e840f9c711f50a74437d1b3856222db03.tar.gz coreboot-0d19289e840f9c711f50a74437d1b3856222db03.tar.bz2 coreboot-0d19289e840f9c711f50a74437d1b3856222db03.zip | |
arch/x86/ioapic: use uintptr_t for IOAPIC base address
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/northbridge.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index bc5439dc8280..430eeef6f620 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -87,7 +87,7 @@ static void nb_read_resources(struct device *dev) static void northbridge_init(struct device *dev) { - register_new_ioapic((u8 *)IO_APIC2_ADDR); + register_new_ioapic(IO_APIC2_ADDR); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) @@ -119,7 +119,7 @@ static unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long curr ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; - ivhd_ioapic->handle = get_ioapic_id(VIO_APIC_VADDR); + ivhd_ioapic->handle = get_ioapic_id(IO_APIC_ADDR); ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); @@ -128,7 +128,7 @@ static unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long curr ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; ivhd_ioapic->reserved = 0x0000; ivhd_ioapic->dte_setting = 0x00; - ivhd_ioapic->handle = get_ioapic_id((u8 *)IO_APIC2_ADDR); + ivhd_ioapic->handle = get_ioapic_id(IO_APIC2_ADDR); ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; current += sizeof(ivrs_ivhd_special_t); |