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author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 09:45:19 +0100 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-12-01 10:27:52 +0000 |
commit | 2fb6f68ef09358aa6f2550519e71a1d74702d5ef (patch) | |
tree | 68e32aec7db7d4d2bc6329691ad44f72d14d1244 /src/northbridge | |
parent | ea6a3b488c238f9b79ee3aeaedaf6b06e2dc4023 (diff) | |
download | coreboot-2fb6f68ef09358aa6f2550519e71a1d74702d5ef.tar.gz coreboot-2fb6f68ef09358aa6f2550519e71a1d74702d5ef.tar.bz2 coreboot-2fb6f68ef09358aa6f2550519e71a1d74702d5ef.zip |
nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index df5526c24464..31e3de46dc31 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -200,7 +200,7 @@ static void pci_domain_ssdt(const struct device *dev) set_above_4g_pci(dev); } -static struct device_operations pci_domain_ops = { +struct device_operations gm45_pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, .init = mch_domain_init, @@ -210,22 +210,12 @@ static struct device_operations pci_domain_ops = { .acpi_name = northbridge_acpi_name, }; -static struct device_operations cpu_bus_ops = { +struct device_operations gm45_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - static void gm45_init(void *const chip_info) { int dev, fn, bit_base; @@ -265,6 +255,5 @@ static void gm45_init(void *const chip_info) struct chip_operations northbridge_intel_gm45_ops = { CHIP_NAME("Intel GM45 Northbridge") - .enable_dev = enable_dev, .init = gm45_init, }; |