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| author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-16 14:17:02 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-18 16:36:33 +0000 |
| commit | 58a5374d5fbf2ddccbd5a2b156ac1a4b44b91522 (patch) | |
| tree | 99683e76ff1ecbb30a5aa63e2707c40b5c38e5ca /src/northbridge | |
| parent | 61f22cff5916dc528690721aa3aaa88f9c6576ad (diff) | |
| download | coreboot-58a5374d5fbf2ddccbd5a2b156ac1a4b44b91522.tar.gz coreboot-58a5374d5fbf2ddccbd5a2b156ac1a4b44b91522.tar.bz2 coreboot-58a5374d5fbf2ddccbd5a2b156ac1a4b44b91522.zip | |
sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree
Since the PCIe root ports in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.
TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are
visible and working.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chipset.cb | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 38a53d54e1d1..c3c35c1ace94 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -27,14 +27,14 @@ chip northbridge/intel/sandybridge device pci 19.0 alias gbe off end # Intel Gigabit Ethernet device pci 1a.0 alias ehci2 off end # USB2 EHCI #2 device pci 1b.0 alias hda off end # High Definition Audio - device pci 1c.0 alias pcie_rp1 off end # PCIe Port #1 - device pci 1c.1 alias pcie_rp2 off end # PCIe Port #2 - device pci 1c.2 alias pcie_rp3 off end # PCIe Port #3 - device pci 1c.3 alias pcie_rp4 off end # PCIe Port #4 - device pci 1c.4 alias pcie_rp5 off end # PCIe Port #5 - device pci 1c.5 alias pcie_rp6 off end # PCIe Port #6 - device pci 1c.6 alias pcie_rp7 off end # PCIe Port #7 - device pci 1c.7 alias pcie_rp8 off end # PCIe Port #8 + device pci 1c.0 alias pcie_rp1 off ops bd82x6x_pcie_rp_ops end # PCIe Port #1 + device pci 1c.1 alias pcie_rp2 off ops bd82x6x_pcie_rp_ops end # PCIe Port #2 + device pci 1c.2 alias pcie_rp3 off ops bd82x6x_pcie_rp_ops end # PCIe Port #3 + device pci 1c.3 alias pcie_rp4 off ops bd82x6x_pcie_rp_ops end # PCIe Port #4 + device pci 1c.4 alias pcie_rp5 off ops bd82x6x_pcie_rp_ops end # PCIe Port #5 + device pci 1c.5 alias pcie_rp6 off ops bd82x6x_pcie_rp_ops end # PCIe Port #6 + device pci 1c.6 alias pcie_rp7 off ops bd82x6x_pcie_rp_ops end # PCIe Port #7 + device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end # PCIe Port #8 device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 device pci 1e.0 alias pci_bridge off end # PCI bridge device pci 1f.0 alias lpc on end # LPC bridge |