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| author | Furquan Shaikh <furquan@google.com> | 2020-06-15 17:22:02 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-17 20:54:32 +0000 |
| commit | 5edbb1c5d917ae27aa8c869a92f3f8750dea9845 (patch) | |
| tree | 6d4a891ced5ea77980a865b1e6b89ec6a8fb3f15 /src/northbridge | |
| parent | 3cd3cb6f33cbbd18f9acac01ca5008e2dfb76242 (diff) | |
| download | coreboot-5edbb1c5d917ae27aa8c869a92f3f8750dea9845.tar.gz coreboot-5edbb1c5d917ae27aa8c869a92f3f8750dea9845.tar.bz2 coreboot-5edbb1c5d917ae27aa8c869a92f3f8750dea9845.zip | |
Revert "soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run"
This reverts commit d5f1e0f9734273f79ebd313bb6a17eda04c22c11.
Reason for revert: FSP-S is now fixed to not touch the SPI
configuration registers. Thus, coreboot does not need to reconfigure
SPI after FSP-S has run.
BUG=b:153506142
TEST=Verified that SPI configuration registers look the same before
and after FSP-S has run. em100 works fine without any additional
changes in coreboot to reconfigure SPI.
Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions