diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-02 06:14:50 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-03 17:33:41 +0000 |
| commit | 825646e6431b51bd45349dbd2cb1d607e2eecae1 (patch) | |
| tree | 642cf8f160a6108f9fa3844d203c4469819d118b /src/northbridge | |
| parent | 641e0f68417bfff7fe11b854df04987a6c31c81b (diff) | |
| download | coreboot-825646e6431b51bd45349dbd2cb1d607e2eecae1.tar.gz coreboot-825646e6431b51bd45349dbd2cb1d607e2eecae1.tar.bz2 coreboot-825646e6431b51bd45349dbd2cb1d607e2eecae1.zip | |
intel/haswell: Move stage_cache support function
Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.
Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE.
Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/ram_calc.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index bdf54d243548..3a63afcde6a1 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <cbmem.h> +#include <stage_cache.h> #include "haswell.h" static uintptr_t smm_region_start(void) @@ -34,3 +35,16 @@ void *cbmem_top(void) { return (void *)smm_region_start(); } + +/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); +} |