diff options
| author | Shawn Nematbakhsh <shawnn@google.com> | 2013-05-08 11:41:04 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-01 23:19:38 +0100 |
| commit | 932fbd659ac7bea41e977f5fb5315fcfc93d36dd (patch) | |
| tree | b097680c82dc5eccebec5cc269cb3e14d4e304f2 /src/northbridge | |
| parent | ce22cd066bfa1c3c2c24ef6c6759620c52aeba22 (diff) | |
| download | coreboot-932fbd659ac7bea41e977f5fb5315fcfc93d36dd.tar.gz coreboot-932fbd659ac7bea41e977f5fb5315fcfc93d36dd.tar.bz2 coreboot-932fbd659ac7bea41e977f5fb5315fcfc93d36dd.zip | |
Add DDR refresh config to pei data structure.
Allow platform customized DDR config, including forcing refresh rate to
2x.
Change-Id: I311ae7ddf25142153c94a3fc3fb0a36e03f50ab2
Reviewed-on: https://gerrit.chromium.org/gerrit/50476
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4213
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/pei_data.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index d317515cf0f0..5e0ff0f56b46 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -121,6 +121,14 @@ struct pei_data * 2 2N */ int nmode; + /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows + * for DIMM SPD data to specify whether double-rate is required for + * extended operating temperature range. + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate + */ + int ddr_refresh_rate_config; } __attribute__((packed)); #endif |