diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 11:39:58 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-05 14:22:12 +0000 |
| commit | 98c92570d9bb363740ae1b2cbbefc3c0f2404cb4 (patch) | |
| tree | 4d23f557990d8edb3edb1b09e2be3cd609b6acd7 /src/northbridge | |
| parent | 6f573217a0920b18ea9febd9c6696a01b0f7c082 (diff) | |
| download | coreboot-98c92570d9bb363740ae1b2cbbefc3c0f2404cb4.tar.gz coreboot-98c92570d9bb363740ae1b2cbbefc3c0f2404cb4.tar.bz2 coreboot-98c92570d9bb363740ae1b2cbbefc3c0f2404cb4.zip | |
cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.
This removes the need for a magic lapic in the devicetree.
Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/gm45/chip.h | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/northbridge.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 6 |
4 files changed, 21 insertions, 0 deletions
diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 0d09bb40efc9..76ceccac6e8a 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -19,6 +19,7 @@ struct northbridge_intel_gm45_config { * Maximum PCI mmio size in MiB. */ u16 pci_mmio_size; + int slfm; }; #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 31e3de46dc31..c6fa0e065ca7 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -7,6 +7,7 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/cpu.h> +#include <cpu/intel/speedstep.h> #include <cpu/intel/smm_reloc.h> #include <device/device.h> #include <device/pci_def.h> @@ -257,3 +258,10 @@ struct chip_operations northbridge_intel_gm45_ops = { CHIP_NAME("Intel GM45 Northbridge") .init = gm45_init, }; + +bool northbridge_support_slfm(void) +{ + struct device *gmch = __pci_0_00_0; + struct northbridge_intel_gm45_config *config = gmch->chip_info; + return config->slfm == 1; +} diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index c175576d3a86..00276562d822 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -10,6 +10,7 @@ #include <device/pci_ids.h> #include <acpi/acpi.h> #include <cpu/intel/smm_reloc.h> +#include <cpu/intel/speedstep.h> #include "i945.h" static void mch_domain_read_resources(struct device *dev) @@ -164,3 +165,8 @@ struct device_operations i945_cpu_bus_ops = { struct chip_operations northbridge_intel_i945_ops = { CHIP_NAME("Intel i945 Northbridge") }; + +bool northbridge_support_slfm(void) +{ + return false; +} diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index da046d169706..cfa57ada49c3 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -12,6 +12,7 @@ #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/intel/smm_reloc.h> +#include <cpu/intel/speedstep.h> static void mch_domain_read_resources(struct device *dev) { @@ -194,3 +195,8 @@ struct chip_operations northbridge_intel_x4x_ops = { CHIP_NAME("Intel 4-Series Northbridge") .init = x4x_init, }; + +bool northbridge_support_slfm(void) +{ + return false; +} |