timestamps: Rename timestamps to make names more consistent

This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

10 files changed, 20 insertions, 20 deletions

diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 4a8cf9057a0c..22a14ae3398a 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -1704,7 +1704,7 @@ void sdram_initialize(void)
 	if (!e7505_mch_is_ready()) {
 
 		/* The real MCH initialisation. */
-		timestamp_add_now(TS_BEFORE_INITRAM);
+		timestamp_add_now(TS_INITRAM_START);
 
 		sdram_set_registers(memctrl);
 		sdram_set_spd_registers(memctrl);
@@ -1713,7 +1713,7 @@ void sdram_initialize(void)
 		/* Hook for post ECC scrub settings and debug. */
 		sdram_post_ecc(memctrl);
 
-		timestamp_add_now(TS_AFTER_INITRAM);
+		timestamp_add_now(TS_INITRAM_END);
 	}
 
 	printk(BIOS_DEBUG, "SDRAM is up.\n");
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 6e505da7bc5e..35d71c009f9f 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1695,7 +1695,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
 
 	int ch;
 
-	timestamp_add_now(TS_BEFORE_INITRAM);
+	timestamp_add_now(TS_INITRAM_START);
 
 	/* Wait for some bit, maybe TXT clear. */
 	if (sysinfo->txt_enabled) {
@@ -1803,5 +1803,5 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
 	raminit_thermal(sysinfo);
 	init_igd(sysinfo);
 
-	timestamp_add_now(TS_AFTER_INITRAM);
+	timestamp_add_now(TS_INITRAM_END);
 }
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index e1a933766a87..533676940468 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -405,13 +405,13 @@ void perform_raminit(const int s3resume)
 	pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
 	pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
 
-	timestamp_add_now(TS_BEFORE_INITRAM);
+	timestamp_add_now(TS_INITRAM_START);
 
 	copy_spd(&pei_data, &spdi);
 
 	sdram_initialize(&pei_data);
 
-	timestamp_add_now(TS_AFTER_INITRAM);
+	timestamp_add_now(TS_INITRAM_END);
 
 	post_code(0x3b);
 
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index e5d377e0c21c..93cbeb91e43b 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -1004,7 +1004,7 @@ void __weak disable_spd(void) { }
 
 void sdram_initialize(int s3resume)
 {
-	timestamp_add_now(TS_BEFORE_INITRAM);
+	timestamp_add_now(TS_INITRAM_START);
 	enable_spd();
 
 	dump_spd_registers();
@@ -1013,5 +1013,5 @@ void sdram_initialize(int s3resume)
 	sdram_enable();
 
 	disable_spd();
-	timestamp_add_now(TS_AFTER_INITRAM);
+	timestamp_add_now(TS_INITRAM_END);
 }
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index e168f7ce9447..982099e89955 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2683,7 +2683,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
 {
 	struct sys_info sysinfo;
 
-	timestamp_add_now(TS_BEFORE_INITRAM);
+	timestamp_add_now(TS_INITRAM_START);
 	printk(BIOS_DEBUG, "Setting up RAM controller.\n");
 
 	memset(&sysinfo, 0, sizeof(sysinfo));
@@ -2783,5 +2783,5 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses)
 	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
 	sdram_setup_processor_side();
-	timestamp_add_now(TS_AFTER_INITRAM);
+	timestamp_add_now(TS_INITRAM_END);
 }
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c
index 242100b80052..f7177826e544 100644
--- a/src/northbridge/intel/ironlake/romstage.c
+++ b/src/northbridge/intel/ironlake/romstage.c
@@ -42,7 +42,7 @@ void mainboard_romstage_entry(void)
 
 	early_thermal_init();
 
-	timestamp_add_now(TS_BEFORE_INITRAM);
+	timestamp_add_now(TS_INITRAM_START);
 
 	chipset_init(s3resume);
 
@@ -52,7 +52,7 @@ void mainboard_romstage_entry(void)
 
 	raminit(s3resume, spd_addrmap);
 
-	timestamp_add_now(TS_AFTER_INITRAM);
+	timestamp_add_now(TS_INITRAM_END);
 
 	intel_early_me_status();
 
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index a98ae99ac8a6..03058ec2b538 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -50,9 +50,9 @@ void mainboard_romstage_entry(void)
 	get_mb_spd_addrmap(&spd_addrmap[0]);
 
 	printk(BIOS_DEBUG, "Initializing memory\n");
-	timestamp_add_now(TS_BEFORE_INITRAM);
+	timestamp_add_now(TS_INITRAM_START);
 	sdram_initialize(boot_path, spd_addrmap);
-	timestamp_add_now(TS_AFTER_INITRAM);
+	timestamp_add_now(TS_INITRAM_END);
 	printk(BIOS_DEBUG, "Memory initialized\n");
 
 	post_code(0x31);
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index a3e701686ffe..9082f8a7d3b7 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -298,7 +298,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
 	size_t mrc_size;
 	ramctr_timing *ctrl_cached = NULL;
 
-	timestamp_add_now(TS_BEFORE_INITRAM);
+	timestamp_add_now(TS_INITRAM_START);
 
 	mchbar_setbits32(SAPMCTL, 1 << 0);
 
@@ -460,7 +460,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
 
 	report_memory_config();
 
-	timestamp_add_now(TS_AFTER_INITRAM);
+	timestamp_add_now(TS_INITRAM_END);
 
 	cbmem_was_inited = !cbmem_recovery(s3resume);
 	if (!fast_boot)
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index c52203a14eb1..fbb2b6eebbb3 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -364,9 +364,9 @@ void perform_raminit(int s3resume)
 	disable_p2p();
 
 	pei_data.boot_mode = s3resume ? 2 : 0;
-	timestamp_add_now(TS_BEFORE_INITRAM);
+	timestamp_add_now(TS_INITRAM_START);
 	sdram_initialize(&pei_data);
-	timestamp_add_now(TS_AFTER_INITRAM);
+	timestamp_add_now(TS_INITRAM_END);
 
 	/* Sanity check mrc_var location by verifying a known field */
 	mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE;
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 460916b421df..2f844a5b365d 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -566,7 +566,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 	int fast_boot, cbmem_was_inited;
 	size_t mrc_size;
 
-	timestamp_add_now(TS_BEFORE_INITRAM);
+	timestamp_add_now(TS_INITRAM_START);
 	printk(BIOS_DEBUG, "Setting up RAM controller.\n");
 
 	pci_write_config8(HOST_BRIDGE, 0xdf, 0xff);
@@ -638,7 +638,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 
 	pci_or_config8(HOST_BRIDGE, 0xf4, 1);
 
-	timestamp_add_now(TS_AFTER_INITRAM);
+	timestamp_add_now(TS_INITRAM_END);
 
 	printk(BIOS_DEBUG, "RAM initialization finished.\n");