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| author | Elyes Haouas <ehaouas@noos.fr> | 2022-12-28 12:33:58 +0100 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-01-04 12:39:32 +0000 |
| commit | f82e68c900151efae572e3bc19690e978b82ca1b (patch) | |
| tree | fb3709fdb6601c2417baac81219d71fe999c433f /src/northbridge | |
| parent | af6cd3f0b44a39bb6387c8218e5872afb74fcc3f (diff) | |
| download | coreboot-f82e68c900151efae572e3bc19690e978b82ca1b.tar.gz coreboot-f82e68c900151efae572e3bc19690e978b82ca1b.tar.bz2 coreboot-f82e68c900151efae572e3bc19690e978b82ca1b.zip | |
spd.h: Move enum ddr3_module_type to ddr3.h
Move specific enum ddr3_module_type to <device/dram/ddr3.h>.
Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell_mrc/raminit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 533676940468..7adae9e64cff 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -261,7 +261,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->mod_id = (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) | (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff); - dimm->mod_type = DDR3_SPD_SODIMM; + dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a308d0730568..aec300b5ef31 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -433,7 +433,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->mod_id = /* bytes 117/118 */ (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); - dimm->mod_type = DDR3_SPD_SODIMM; + dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } @@ -457,7 +457,7 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->mod_id = /* bytes 117/118 */ (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); - dimm->mod_type = DDR3_SPD_SODIMM; + dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; } |