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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2021-11-30 18:31:26 +0100 |
|---|---|---|
| committer | Patrick Georgi <patrick@coreboot.org> | 2021-12-06 12:37:30 +0000 |
| commit | c7f0bca9c23ac8d96ffc5ec0fcaddf9190d7dbff (patch) | |
| tree | 96491da8c71553727dcd7e3e2627d4fe02854681 /src/security/intel | |
| parent | 9f37647b0486e2a2566bf39ea39992cc20123354 (diff) | |
| download | coreboot-c7f0bca9c23ac8d96ffc5ec0fcaddf9190d7dbff.tar.gz coreboot-c7f0bca9c23ac8d96ffc5ec0fcaddf9190d7dbff.tar.bz2 coreboot-c7f0bca9c23ac8d96ffc5ec0fcaddf9190d7dbff.zip | |
security/intel: Use defines for segment registers
Change-Id: I6f11039bafa3800d59d61defa8824ae962224c9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59763
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/security/intel')
| -rw-r--r-- | src/security/intel/txt/getsec_enteraccs.S | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index be3a1b4f0ba6..09f9f389e653 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -3,6 +3,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> +#include <arch/ram_segs.h> #include "getsec_mtrr_setup.inc" @@ -252,10 +253,10 @@ cond_clear_var_mtrrs: lgdt -48(%ebp) /* Set cs */ - ljmp $0x10, $1f + ljmp $RAM_CODE_SEG, $1f 1: /* Fix segment registers */ - movl $0x18, %eax + movl $RAM_DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss |