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| author | Shelley Chen <shchen@google.com> | 2020-10-16 12:30:05 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-10-20 23:25:31 +0000 |
| commit | 1fed53f08a8099e03e352034b1265cc7b2fd427a (patch) | |
| tree | 6c811978e543ac9bead5375e6cc4b56c72a37b3b /src/security/vboot/Makefile.inc | |
| parent | 9f8ac64baef21dc0be7d1b54c998561dcced0d89 (diff) | |
| download | coreboot-1fed53f08a8099e03e352034b1265cc7b2fd427a.tar.gz coreboot-1fed53f08a8099e03e352034b1265cc7b2fd427a.tar.bz2 coreboot-1fed53f08a8099e03e352034b1265cc7b2fd427a.zip | |
mrc_cache: Move mrc_cache_*_hash functions into mrc_cache driver
This CL would remove these calls from fsp 2.0. Platforms that select
MRC_STASH_TO_CBMEM, updating the TPM NVRAM space is moved from
romstage (when data stashed to CBMEM) to ramstage (when data is
written back to SPI flash.
BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami
Change-Id: I3088ca6927c7dbc65386c13e868afa0462086937
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/security/vboot/Makefile.inc')
| -rw-r--r-- | src/security/vboot/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d4dabe249306..4cf809016a8c 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -119,6 +119,7 @@ ramstage-y += common.c postcar-y += common.c romstage-$(CONFIG_MRC_SAVE_HASH_IN_TPM) += mrc_cache_hash_tpm.c +ramstage-$(CONFIG_MRC_SAVE_HASH_IN_TPM) += mrc_cache_hash_tpm.c ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) |