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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-10-28 10:11:16 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-01 15:59:54 +0000 |
| commit | 083aa9ecf766fddd27e53f9476ca817ea1a2034b (patch) | |
| tree | 5ac83ead3fa7ac9f0e90fb38e2d490bd9202b30c /src/security | |
| parent | af207a5279e91afab912c4c9ed140e2aec8808b3 (diff) | |
| download | coreboot-083aa9ecf766fddd27e53f9476ca817ea1a2034b.tar.gz coreboot-083aa9ecf766fddd27e53f9476ca817ea1a2034b.tar.bz2 coreboot-083aa9ecf766fddd27e53f9476ca817ea1a2034b.zip | |
security/intel/txt: Get addr bits at runtime
This removes the need for a Kconfig value.
Change-Id: Ia9f39aa1c7fb9a64c2e5412bac6e2600b222a635
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/security')
| -rw-r--r-- | src/security/intel/txt/getsec_mtrr_setup.inc | 14 | ||||
| -rw-r--r-- | src/security/intel/txt/getsec_sclean.S | 2 |
2 files changed, 11 insertions, 5 deletions
diff --git a/src/security/intel/txt/getsec_mtrr_setup.inc b/src/security/intel/txt/getsec_mtrr_setup.inc index 15e8cc17ad83..44471ebea852 100644 --- a/src/security/intel/txt/getsec_mtrr_setup.inc +++ b/src/security/intel/txt/getsec_mtrr_setup.inc @@ -3,8 +3,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) - /* * Configure the MTRRs to cache the BIOS ACM. No general-purpose * registers are preserved. Inputs are taken from SSE registers: @@ -16,6 +14,16 @@ */ .macro SET_UP_MTRRS_FOR_BIOS_ACM + /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ + movl $0x80000008, %eax + cpuid + movb %al, %cl + sub $32, %cl + movl $1, %edx + shl %cl, %edx + subl $1, %edx + movl %edx, %edi /* %edi contains the MTRR_HIGH_MASK */ + /* Get the number of variable MTRRs */ movl $(MTRR_CAP_MSR), %ecx rdmsr @@ -56,7 +64,7 @@ body_allocate_var_mtrrs: movd %eax, %xmm1 /* Program MTRR mask */ - movl MTRR_HIGH_MASK, %edx + movl %edi, %edx xorl %eax, %eax subl %ebx, %eax /* %eax = 4GIB - size to cache */ orl $(MTRR_PHYS_MASK_VALID), %eax diff --git a/src/security/intel/txt/getsec_sclean.S b/src/security/intel/txt/getsec_sclean.S index e240a2faaa36..0944e158e232 100644 --- a/src/security/intel/txt/getsec_sclean.S +++ b/src/security/intel/txt/getsec_sclean.S @@ -6,8 +6,6 @@ #include "getsec_mtrr_setup.inc" -#define MTRR_HIGH_MASK $((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) - #define NO_EVICT_MODE 0x2e0 .align 4 |