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| author | Elyes Haouas <ehaouas@noos.fr> | 2022-07-10 21:00:06 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-20 13:16:52 +0000 |
| commit | ef26dee2f44f6134a49d6b83dc2a47bf7b24b533 (patch) | |
| tree | 3823e46e4de3710d4f66c6101bb2e095c8059367 /src/security | |
| parent | eb8a81fca0b1416d889fed3c8b5c24c8d7f35f30 (diff) | |
| download | coreboot-ef26dee2f44f6134a49d6b83dc2a47bf7b24b533.tar.gz coreboot-ef26dee2f44f6134a49d6b83dc2a47bf7b24b533.tar.bz2 coreboot-ef26dee2f44f6134a49d6b83dc2a47bf7b24b533.zip | |
treewide: Remove unused <cpu/x86/msr.h>
Change-Id: I187c2482dd82c6c6d1fe1cbda71710ae1a2f54ad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/security')
| -rw-r--r-- | src/security/intel/txt/ramstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 265f81e62d19..744b05e410b0 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -7,7 +7,6 @@ #include <cbfs.h> #include <console/console.h> #include <cpu/intel/common/common.h> -#include <cpu/x86/msr.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <security/intel/cbnt/cbnt.h> |