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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-04 21:06:04 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-05 19:39:22 +0000 |
| commit | 144c7aa34bffba7b65566e037f0588ace8b00eba (patch) | |
| tree | c46e83920de270267acb6d3fc750d8b432c89ad7 /src/soc/amd/cezanne/Makefile.inc | |
| parent | afc4978ede7c86cddb0552ebc8da046244affe61 (diff) | |
| download | coreboot-144c7aa34bffba7b65566e037f0588ace8b00eba.tar.gz coreboot-144c7aa34bffba7b65566e037f0588ace8b00eba.tar.bz2 coreboot-144c7aa34bffba7b65566e037f0588ace8b00eba.zip | |
soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tables
This function will be used to add some SSDTs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia88cb5ea483850a8659f3bae8040c82eb2735d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index e51a6163a87b..ebdad458a623 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -32,6 +32,7 @@ romstage-y += uart.c ramstage-y += i2c.c ramstage-y += acpi.c +ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += data_fabric.c |