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| author | Rob Barnes <robbarnes@google.com> | 2021-12-17 10:37:43 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-20 17:52:50 +0000 |
| commit | 4454c9af3c3d44c4ea3c3dfa9eb58c59385e3778 (patch) | |
| tree | 519d6e26583b63e81eba03ed55b378a8ab1c2a2e /src/soc/amd/cezanne/Makefile.inc | |
| parent | 57af68fec90bb44449e33066d641dd5f2108b83e (diff) | |
| download | coreboot-4454c9af3c3d44c4ea3c3dfa9eb58c59385e3778.tar.gz coreboot-4454c9af3c3d44c4ea3c3dfa9eb58c59385e3778.tar.bz2 coreboot-4454c9af3c3d44c4ea3c3dfa9eb58c59385e3778.zip | |
soc/amd/cezanne: Correct S0i3 verstage softfuse bit
PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40.
BUG=b:202397678
BRANCH=None
TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP.
Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index a05da8dc7616..050ba44be98c 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -111,7 +111,7 @@ PSP_SOFTFUSE_BITS += 29 endif ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) -PSP_SOFTFUSE_BITS += 40 +PSP_SOFTFUSE_BITS += 58 endif # Use additional Soft Fuse bits specified in Kconfig |