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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-03-26 00:13:51 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-03-29 19:52:01 +0000 |
| commit | 793f3717b4fd430f03455bdbbd071d5f7d104b57 (patch) | |
| tree | 98d502d6cb0e60bd50cfd8526cee6dad7521c7a5 /src/soc/amd/cezanne/Makefile.inc | |
| parent | a228279ed795cb9fe89b38a4b5cbe40a38662767 (diff) | |
| download | coreboot-793f3717b4fd430f03455bdbbd071d5f7d104b57.tar.gz coreboot-793f3717b4fd430f03455bdbbd071d5f7d104b57.tar.bz2 coreboot-793f3717b4fd430f03455bdbbd071d5f7d104b57.zip | |
soc/amd/cezanne,picasso: rename fsp_params.c to fsp_s_params.c
This file populates the UPD-S data structure that gets passed to the
FSP-S, so add that s part to make it a bit clearer which FSP parameters
it'll set up. This is also a preparation to add a fsp_m_params.c file in
the following patches.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53786df0909055e66eac675b5580909b7960944f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 91a16d89ba51..dfa047f852b8 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -33,7 +33,7 @@ ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += data_fabric.c ramstage-y += fch.c -ramstage-y += fsp_params.c +ramstage-y += fsp_s_params.c ramstage-y += gpio.c ramstage-y += pcie_gpp.c ramstage-y += reset.c |