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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-19 14:52:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-24 19:36:48 +0000 |
| commit | 8240cc33ec2d415cf92816e8af4ed6dd47664543 (patch) | |
| tree | 797b0e42e375ff57ab5c5addb49084028a1c7fcc /src/soc/amd/cezanne/Makefile.inc | |
| parent | 5d7c3a4f013d650aab87a71e6468e89586846703 (diff) | |
| download | coreboot-8240cc33ec2d415cf92816e8af4ed6dd47664543.tar.gz coreboot-8240cc33ec2d415cf92816e8af4ed6dd47664543.tar.bz2 coreboot-8240cc33ec2d415cf92816e8af4ed6dd47664543.zip | |
soc/amd/cezanne/Makefile: move setting of PSP soft fuse bit 6
The PSP soft fuse bit 6 doesn't do what the comment above it says. See
NDA document #55758 for details.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic84cf6e1eee30af92cd700dc4bf78290143bf88b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 589e760bf7a8..d631c6349500 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -102,10 +102,10 @@ PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | a PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0xb - See #55758 (NDA) for bit definitions. -PSP_SOFTFUSE_BITS += 28 +PSP_SOFTFUSE_BITS += 28 6 #hardcode post code to eSPI -PSP_SOFTFUSE_BITS += 15 6 +PSP_SOFTFUSE_BITS += 15 # Helper function to return a value with given bit set set-bit=$(call int-shift-left, 1 $(call _toint,$1)) |