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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-14 01:40:50 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-24 18:15:46 +0000 |
| commit | 8d0a609e6d1bfb48de781e7223f73ff979d0ce2e (patch) | |
| tree | d3f40d275aeff99da11287de34bcc1bb62f7a2d6 /src/soc/amd/cezanne/Makefile.inc | |
| parent | 45b0714c89db4487074e87ada13b9886c43d9ccd (diff) | |
| download | coreboot-8d0a609e6d1bfb48de781e7223f73ff979d0ce2e.tar.gz coreboot-8d0a609e6d1bfb48de781e7223f73ff979d0ce2e.tar.bz2 coreboot-8d0a609e6d1bfb48de781e7223f73ff979d0ce2e.zip | |
soc,vendorcode/amd/cezanne: add basic FSP integration
This is a trimmed-down version of the Cezanne FSP integration code, so
for example the UPD definitions are empty, which will be addressed
later. Since coreboot just leaves the UPD values at their default, this
is not a problem during the initial platform bring-up.
Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index a00a9f575c36..46ac199649fb 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -25,11 +25,15 @@ romstage-y += romstage.c romstage-y += uart.c ramstage-y += chip.c +ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += reset.c ramstage-y += uart.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include +CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne + +$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) |