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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-16 20:51:08 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-17 21:32:59 +0000 |
| commit | d5b51beb797700f83f6d894e83679739280d8f11 (patch) | |
| tree | 9671ba734218f26227355c477b3204ff34ea1727 /src/soc/amd/cezanne/Makefile.inc | |
| parent | 81d367feee138798f57ec1217209cb1c28244daa (diff) | |
| download | coreboot-d5b51beb797700f83f6d894e83679739280d8f11.tar.gz coreboot-d5b51beb797700f83f6d894e83679739280d8f11.tar.bz2 coreboot-d5b51beb797700f83f6d894e83679739280d8f11.zip | |
soc/amd/cezanne/graphics: add VBIOS ID remapping for Barcelo
Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI
ID, so we need to implement map_oprom_vendev for the SoC.
BUG=b:193888172
Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 478eeccac325..d693ec6576c8 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -33,7 +33,6 @@ romstage-y += uart.c ramstage-y += i2c.c ramstage-y += acpi.c ramstage-y += cppc.c - ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c @@ -41,6 +40,7 @@ ramstage-y += data_fabric.c ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c +ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += reset.c ramstage-y += root_complex.c |