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| author | Rob Barnes <robbarnes@google.com> | 2021-04-15 17:21:19 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-22 12:43:33 +0000 |
| commit | e09b681e6e574d0d59d260471c1ab91932fed48f (patch) | |
| tree | 0c2271ea925642f44bd6328af5c0c60053045a6d /src/soc/amd/cezanne/Makefile.inc | |
| parent | 03dfd19e6e941a32ae63ce5e20e6fb5438a25b06 (diff) | |
| download | coreboot-e09b681e6e574d0d59d260471c1ab91932fed48f.tar.gz coreboot-e09b681e6e574d0d59d260471c1ab91932fed48f.tar.bz2 coreboot-e09b681e6e574d0d59d260471c1ab91932fed48f.zip | |
guybrush: Add Kconfig for PSP eSPI and port80
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for
cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect
PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus
errors on guybrush.
BUG=b:185514903, b:184356693
TEST=Boot guybrush, observe no port80 codes from PSP
Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 80ce622814fd..1264a249d36a 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -80,6 +80,14 @@ CEZANNE_FWM_POSITION=$(call int-add, \ FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y) +PSP_SOFTFUSE_BITS += 15 +endif + ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) # Enable secure debug unlock PSP_SOFTFUSE_BITS += 0 @@ -122,9 +130,6 @@ APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 6 -#hardcode post code to eSPI -PSP_SOFTFUSE_BITS += 15 - # Helper function to return a value with given bit set set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ |