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| author | Raul E Rangel <rrangel@chromium.org> | 2022-02-01 11:12:33 -0700 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-02-02 23:31:51 +0000 |
| commit | fa4d0510ea4952829114ff7ca877749bed049094 (patch) | |
| tree | eb5e832188897ff41c4e4d9e1600a6ddceea145e /src/soc/amd/cezanne/Makefile.inc | |
| parent | 21fdd44db037e4751f9793a2fcf4a3646a70fd88 (diff) | |
| download | coreboot-fa4d0510ea4952829114ff7ca877749bed049094.tar.gz coreboot-fa4d0510ea4952829114ff7ca877749bed049094.tar.bz2 coreboot-fa4d0510ea4952829114ff7ca877749bed049094.zip | |
soc/amd/cezanne: Rename PSP_POSTCODES_ON_ESPI to PSP_INIT_ESPI
This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It
doesn't control if port 80s are written. This flag also doesn't
currently control LPC init. The PSP is currently hard coded to remove
any LPC init.
BUG=b:215425753
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 5fda4b0b826d..5708baa0e328 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -94,7 +94,7 @@ ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) PSP_SOFTFUSE_BITS += 7 endif -ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y) +ifeq ($(CONFIG_PSP_INIT_ESPI),y) PSP_SOFTFUSE_BITS += 15 endif |