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| author | Julian Schroeder <julianmarcusschroeder@gmail.com> | 2021-07-09 16:10:08 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-15 21:39:04 +0000 |
| commit | 577e146895d489d809b4d41da7f6f2d7428143a2 (patch) | |
| tree | 963579f26d4c4d179ad797c3ed1fb48f9b0048a6 /src/soc/amd/cezanne/acpi.c | |
| parent | 82e2f3229ea752f76deeba3b3c511a53906e6acc (diff) | |
| download | coreboot-577e146895d489d809b4d41da7f6f2d7428143a2.tar.gz coreboot-577e146895d489d809b4d41da7f6f2d7428143a2.tar.bz2 coreboot-577e146895d489d809b4d41da7f6f2d7428143a2.zip | |
soc/amd/cezanne: add ACPI CPPC support for AMD
This leverages the existing Collaborative Processor Performance Control
(CPPC) support and adds CPPC init for AMD/Cezanne.
BUG=b:185814875
TEST=under Linux/ChromeOS, acpidump ssdt2, find expected CPPC entries
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne/acpi.c')
| -rw-r--r-- | src/soc/amd/cezanne/acpi.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 6e2ae9ca0f4a..3b3a88befe86 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -19,6 +19,7 @@ #include <soc/msr.h> #include <types.h> #include "chip.h" +#include <soc/cppc.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -358,6 +359,8 @@ void generate_cpu_entries(const struct device *device) acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, CSD_HW_ALL, 0); + generate_cppc_entries(cpu); + acpigen_pop_len(); } |