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| author | Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> | 2021-07-20 05:21:54 -0700 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-08-05 15:54:50 +0000 |
| commit | 8d354283315d6dd32f20aa8a53fe87b2352ff956 (patch) | |
| tree | 97070742f9fc1718ae20c4bb9b594091637dc7c4 /src/soc/amd/cezanne/agesa_acpi.c | |
| parent | f934fae03215affaa09bd45d95fc6a785eacf533 (diff) | |
| download | coreboot-8d354283315d6dd32f20aa8a53fe87b2352ff956.tar.gz coreboot-8d354283315d6dd32f20aa8a53fe87b2352ff956.tar.bz2 coreboot-8d354283315d6dd32f20aa8a53fe87b2352ff956.zip | |
soc/amd/cezanne: Generate IVRS for cezanne
Generate IVRS for cezanne using common IVRS generation code.
BUG=b:190515051
TEST=Build cezanne coreboot image. Compare IVRS table with agesa
generated tables.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ie15addba62ec7da25a7452512b6871e46c61b0a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne/agesa_acpi.c')
| -rw-r--r-- | src/soc/amd/cezanne/agesa_acpi.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/agesa_acpi.c b/src/soc/amd/cezanne/agesa_acpi.c index 35114a1a60f1..47ca5f23754a 100644 --- a/src/soc/amd/cezanne/agesa_acpi.c +++ b/src/soc/amd/cezanne/agesa_acpi.c @@ -10,8 +10,17 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { + acpi_ivrs_t *ivrs; + /* add ALIB SSDT from HOB */ current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); + /* IVRS */ + current = ALIGN(current, 8); + ivrs = (acpi_ivrs_t *) current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); + return current; } |