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| author | Zheng Bao <fishbaozi@gmail.com> | 2021-12-06 23:09:37 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 23:57:06 +0000 |
| commit | 8b54c0e04bc3488a6479180b3cb9547b4e0fc763 (patch) | |
| tree | ad204fae0fa75a162b8f44a5778b895564fc673c /src/soc/amd/cezanne/chip.h | |
| parent | 2a404b599b3385b3246a2ee20844d2bc7a428035 (diff) | |
| download | coreboot-8b54c0e04bc3488a6479180b3cb9547b4e0fc763.tar.gz coreboot-8b54c0e04bc3488a6479180b3cb9547b4e0fc763.tar.bz2 coreboot-8b54c0e04bc3488a6479180b3cb9547b4e0fc763.zip | |
soc/amd/cezanne: FSP: Add UPD entry for eDP tuning
The FSP gets these values from the UPD and sets the internal values.
The document about eDP tuning is attached in issue tracker of this
ticket, at the issue tracker b/203061533#comment6.
BUG=b:203061533
Cq-Depend: chrome-internal:4303901
Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/cezanne/chip.h')
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index e54957964447..d007a84c980c 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -106,6 +106,19 @@ struct soc_amd_cezanne_config { uint8_t usb_phy_custom; struct usb_phy_config usb_phy; + + /* eDP phy tuning settings */ + uint8_t edp_phy_override; + /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ + uint8_t edp_physel; + + struct { + uint8_t dp_vs_pemph_level; + uint8_t tx_eq_main; + uint8_t tx_eq_pre; + uint8_t tx_eq_post; + uint8_t tx_vboost_lvl; + } edp_tuningset; }; #endif /* CEZANNE_CHIP_H */ |