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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-08 22:25:19 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-21 22:12:06 +0000 |
| commit | d0b5164cd0980c078323792bd47c3aee6438e9b8 (patch) | |
| tree | 950c09e5e539c8de744e1f6547c82dd9dbd9eaec /src/soc/amd/cezanne/chip.h | |
| parent | 02bfbf44305d1c7d562b9425da53d43d398061cd (diff) | |
| download | coreboot-d0b5164cd0980c078323792bd47c3aee6438e9b8.tar.gz coreboot-d0b5164cd0980c078323792bd47c3aee6438e9b8.tar.bz2 coreboot-d0b5164cd0980c078323792bd47c3aee6438e9b8.zip | |
soc/amd/cezanne: add downcoring and SMT disable settings to devicetree
BUG=b:184162768
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52197
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/chip.h')
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 455de369a4f2..af78ddfd9aba 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -15,6 +15,18 @@ struct soc_amd_cezanne_config { /* Enable S0iX support */ bool s0ix_enable; + + enum { + DOWNCORE_AUTO = 0, + DOWNCORE_1 = 1, /* Run with 1 physical core */ + DOWNCORE_2 = 3, /* Run with 2 physical cores */ + DOWNCORE_3 = 4, /* Run with 3 physical cores */ + DOWNCORE_4 = 6, /* Run with 4 physical cores */ + DOWNCORE_5 = 8, /* Run with 5 physical cores */ + DOWNCORE_6 = 9, /* Run with 6 physical cores */ + DOWNCORE_7 = 10, /* Run with 7 physical cores */ + } downcore_mode; + bool disable_smt; /* disable second thread on all physical cores */ }; #endif /* CEZANNE_CHIP_H */ |