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| author | Robert Zieba <robertzieba@google.com> | 2022-01-19 14:15:24 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-23 19:37:36 +0000 |
| commit | e2bde83a518d10fc6eaa7edca507daf271fdcf0a (patch) | |
| tree | 3321d68cbeff8d57ee3c5b20888e0cc5b27e28bf /src/soc/amd/cezanne/chip.h | |
| parent | e58de0db450027f2f71c468d71b91d0b297a758f (diff) | |
| download | coreboot-e2bde83a518d10fc6eaa7edca507daf271fdcf0a.tar.gz coreboot-e2bde83a518d10fc6eaa7edca507daf271fdcf0a.tar.bz2 coreboot-e2bde83a518d10fc6eaa7edca507daf271fdcf0a.zip | |
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present
before enabling the corresponding gpp_clkx_clock_request_mapping bits
which may cause issues with L1SS. This change sets the corresponding
gpp_clkx_clock_request_mapping to off if the corresponding device is
disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value
when devices are enabled/disabled, checked that physically removing a
device that is marked as enabled also disables the corresponding clk req
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/chip.h')
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 1e59153ef5c8..b01c6c7fa8c0 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -12,6 +12,12 @@ #include <types.h> #include <vendorcode/amd/fsp/cezanne/FspUsb.h> +enum gpp_clk_req { + GPP_CLK_ON, /* GPP clock always on; default */ + GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ + GPP_CLK_OFF, /* GPP clk off */ +}; + struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; u8 i2c_scl_reset; @@ -91,11 +97,7 @@ struct soc_amd_cezanne_config { /* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ - enum { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; /* performance policy for the PCIe links: power consumption vs. link speed */ enum { |