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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-06-02 16:14:39 -0600 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-07 05:18:49 +0000 |
| commit | fec4db954e44a3fd23fedd2f51189c13c985eee9 (patch) | |
| tree | c548c574978d26dbaeb02db1fbfab49a91458ce2 /src/soc/amd/cezanne/chip.h | |
| parent | fcb9716db51ed239fcf2b870b6b5e439e2ffe5c6 (diff) | |
| download | coreboot-fec4db954e44a3fd23fedd2f51189c13c985eee9.tar.gz coreboot-fec4db954e44a3fd23fedd2f51189c13c985eee9.tar.bz2 coreboot-fec4db954e44a3fd23fedd2f51189c13c985eee9.zip | |
soc/amd/cezanne: Configure I2C Pad RX Select through devicetree
Some of the I2C buses are required to operate at different voltage level
compared to other I2C buses eg. I2C bus to Google Security Chip (GSC)
should be at 1.8V level. By default, all the I2C buses are initialized
to operate at 3.3 V. Add support to configure I2C pad RX select through
devicetree and update the concerned devicetree.
BUG=b:188538373
TEST=Build and boot to OS in Guybrush. Ensure that the communication
with GSC is fine. Build Majolica mainboard.
Change-Id: I595a64736fdac0274abffb68c5e521302275b845
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/cezanne/chip.h')
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index df2059a26027..319ce4108e64 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -14,6 +14,7 @@ struct soc_amd_cezanne_config { struct soc_amd_common_config common_config; u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; + u8 i2c_pad_ctrl_rx_sel[I2C_CTRLR_COUNT]; /* Enable S0iX support */ bool s0ix_enable; |