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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-03-10 15:47:00 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-03-11 15:11:20 +0000 |
| commit | a5cdf75f690c2fb48d00df6ab4e7ba2bfd8a4480 (patch) | |
| tree | 93de8f242ab575df4d02b8be7a24713e0099a9ed /src/soc/amd/cezanne/cpu.c | |
| parent | 4626a6684ca02675cebd4e5ceea8ca959cd13472 (diff) | |
| download | coreboot-a5cdf75f690c2fb48d00df6ab4e7ba2bfd8a4480.tar.gz coreboot-a5cdf75f690c2fb48d00df6ab4e7ba2bfd8a4480.tar.bz2 coreboot-a5cdf75f690c2fb48d00df6ab4e7ba2bfd8a4480.zip | |
soc/amd: move warm reset flag function prototypes to common code
Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/cpu.c')
| -rw-r--r-- | src/soc/amd/cezanne/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 6754bba5b928..148dcd8b315d 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> +#include <amdblocks/reset.h> #include <amdblocks/smm.h> #include <console/console.h> #include <cpu/amd/microcode.h> @@ -12,7 +13,6 @@ #include <device/device.h> #include <soc/cpu.h> #include <soc/iomap.h> -#include <soc/reset.h> /* MP and SMM loading initialization */ |