soc/amd/cezanne: add empty ramstage FCH support

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

1 files changed, 11 insertions, 0 deletions

diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
new file mode 100644
index 000000000000..f853ecee93d9
--- /dev/null
+++ b/src/soc/amd/cezanne/fch.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/southbridge.h>
+
+void fch_init(void *chip_info)
+{
+}
+
+void fch_final(void *chip_info)
+{
+}