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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-05-06 17:46:06 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-16 15:21:19 +0000 |
| commit | 2ec44ec95fece227b9dbd7bf70e03c2ddcb5e45a (patch) | |
| tree | 5c671415f8cd07c81669b2b8d9d24b4cbf6b7685 /src/soc/amd/cezanne/fsp_m_params.c | |
| parent | 452baa047a2df868d2d004ea1c938551571adc1f (diff) | |
| download | coreboot-2ec44ec95fece227b9dbd7bf70e03c2ddcb5e45a.tar.gz coreboot-2ec44ec95fece227b9dbd7bf70e03c2ddcb5e45a.tar.bz2 coreboot-2ec44ec95fece227b9dbd7bf70e03c2ddcb5e45a.zip | |
soc/amd/cezanne/fsp_m_params: don't hard-code USB PHY config table size
Use sizeof instead of having a hard-coded struct length.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85dc2fce11d9a670b2037d8a6a694177cfaa2177
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/fsp_m_params.c')
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 8c9e5a15cba8..5b386a531426 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -11,6 +11,7 @@ #include <soc/pci_devs.h> #include <string.h> #include <types.h> +#include <vendorcode/amd/fsp/cezanne/FspUsb.h> #include "chip.h" __weak void mb_pre_fspm(void) @@ -152,7 +153,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->usb_phy = (struct usb_phy_config *)&config->usb_phy; mcfg->usb_phy->Version_Major = 0xd; mcfg->usb_phy->Version_Minor = 0x6; - mcfg->usb_phy->TableLength = 100; + mcfg->usb_phy->TableLength = sizeof(struct usb_phy_config); } else { mcfg->usb_phy = NULL; } |