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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-25 20:45:08 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-27 15:39:08 +0000 |
| commit | 9a24c3f80d477f304a966094ded1ccde4155375c (patch) | |
| tree | 5768782cf71c42f9c53cf41ffa12e7c93263a05d /src/soc/amd/cezanne/fsp_m_params.c | |
| parent | ac2cb4262104ffb2dac229f061480df4a29d8064 (diff) | |
| download | coreboot-9a24c3f80d477f304a966094ded1ccde4155375c.tar.gz coreboot-9a24c3f80d477f304a966094ded1ccde4155375c.tar.bz2 coreboot-9a24c3f80d477f304a966094ded1ccde4155375c.zip | |
soc/amd/cezanne: add devicetree setting for PSPP policy
This allows boards to specify which PSPP policy (basically a dynamic
trade-off between power consumption and PCIe link speed) should be used
and also makes sure that the boards are using the expected PSPP policy
and not just the UPD default from the FSP binary that has already
changed once during the development.
BUG=b:188793754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54930
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/fsp_m_params.c')
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 1e6f5ac26b19..352aeef582aa 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -159,6 +159,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->telemetry_vddcrsocOffset = config->telemetry_vddcrsocoffset; + /* PCIe power vs. speed */ + mcfg->pspp_policy = config->pspp_policy; + mcfg->enable_nb_azalia = devtree_gfx_hda_dev_enabled(); if (config->usb_phy_custom) |