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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-19 21:40:35 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-21 22:13:30 +0000 |
| commit | d3be9ba9023857aaa362e6f2c37766101f7f9d06 (patch) | |
| tree | 1f48acde6ab5352f8a776878b4a77584592057e8 /src/soc/amd/cezanne/fsp_m_params.c | |
| parent | 5dea8271b6e3394c414e4d00398dfcda800e7da8 (diff) | |
| download | coreboot-d3be9ba9023857aaa362e6f2c37766101f7f9d06.tar.gz coreboot-d3be9ba9023857aaa362e6f2c37766101f7f9d06.tar.bz2 coreboot-d3be9ba9023857aaa362e6f2c37766101f7f9d06.zip | |
soc/amd/cezanne: add SMU settings to devicetree
BUG=b:182297189
TEST=none
Cq-Depend: chrome-internal:3772425
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifbcc85cc10d59f1418bbf0ed4a0dc7549d589a26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/fsp_m_params.c')
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index baf4ca8b853e..9d4159d85b65 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -69,5 +69,49 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->ccx_down_core_mode = config->downcore_mode; mcfg->ccx_disable_smt = config->disable_smt; + /* when stt_control isn't 1, FSP will ignore the other stt values */ + mcfg->stt_control = config->stt_control; + mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count; + mcfg->stt_min_limit = config->stt_min_limit; + mcfg->stt_m1 = config->stt_m1; + mcfg->stt_m2 = config->stt_m2; + mcfg->stt_m3 = config->stt_m3; + mcfg->stt_m4 = config->stt_m4; + mcfg->stt_m5 = config->stt_m5; + mcfg->stt_m6 = config->stt_m6; + mcfg->stt_c_apu = config->stt_c_apu; + mcfg->stt_c_gpu = config->stt_c_gpu; + mcfg->stt_c_hs2 = config->stt_c_hs2; + mcfg->stt_alpha_apu = config->stt_alpha_apu; + mcfg->stt_alpha_gpu = config->stt_alpha_gpu; + mcfg->stt_alpha_hs2 = config->stt_alpha_hs2; + mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu; + mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu; + mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2; + mcfg->stt_error_coeff = config->stt_error_coeff; + mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient; + + /* all following fields being 0 is a valid config */ + mcfg->stapm_boost = config->stapm_boost; + mcfg->stapm_time_constant = config->stapm_time_constant; + mcfg->apu_only_sppt_limit = config->apu_only_sppt_limit; + mcfg->sustained_power_limit = config->sustained_power_limit; + mcfg->fast_ppt_limit = config->fast_ppt_limit; + mcfg->slow_ppt_limit = config->slow_ppt_limit; + + /* 0 is default */ + mcfg->smartshift_enable = config->smartshift_enable; + + /* 0 is default */ + mcfg->system_configuration = config->system_configuration; + + /* when cppc_ctrl is 0 the other values won't be used */ + mcfg->cppc_ctrl = config->cppc_ctrl; + mcfg->cppc_perf_limit_max_range = config->cppc_perf_limit_max_range; + mcfg->cppc_perf_limit_min_range = config->cppc_perf_limit_min_range; + mcfg->cppc_epp_max_range = config->cppc_epp_max_range; + mcfg->cppc_epp_min_range = config->cppc_epp_min_range; + mcfg->cppc_preferred_cores = config->cppc_preferred_cores; + fsp_fill_pcie_ddi_descriptors(mcfg); } |