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| author | Zheng Bao <fishbaozi@gmail.com> | 2022-01-27 22:35:53 +0800 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-02-07 18:38:49 +0000 |
| commit | 6bb9e57a8fb4418af24ddfbc45fb597dafa3a95f (patch) | |
| tree | e6c8e508c0a5ec3931f4c9c63e9f6204596a3c12 /src/soc/amd/cezanne/fw.cfg | |
| parent | ab84fd76052c79ba191e22ce4fd9f671748f6a99 (diff) | |
| download | coreboot-6bb9e57a8fb4418af24ddfbc45fb597dafa3a95f.tar.gz coreboot-6bb9e57a8fb4418af24ddfbc45fb597dafa3a95f.tar.bz2 coreboot-6bb9e57a8fb4418af24ddfbc45fb597dafa3a95f.zip | |
soc/amd/cezanne: Add the fw SPL to fw.cfg
SPL: Security Patch Level
The data in SPL is used for FW anti-rollback, preventing rollback of
platform level firmware to older version that are deemed vulnerable
from a security point of view.
BUG=b:216096562
Change-Id: I0aa456b8b4eec506fbb319293f0903b293325cb0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/fw.cfg')
| -rw-r--r-- | src/soc/amd/cezanne/fw.cfg | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 9757d7249e9a..f26e21555ed3 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -28,6 +28,7 @@ UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin +SPL_TABLE_FILE TypeId0x55_SplTableBl_CZN.sbin DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin |