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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-03 21:38:14 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 22:05:59 +0000 |
| commit | 7e703d77b2cb2189863d2a2e87f7de2913e20307 (patch) | |
| tree | 2667898e7a0ab41ad613bf26129e03b071513592 /src/soc/amd/cezanne/include/soc/iomap.h | |
| parent | 757d645cb069f1759303467efb9753fcdd847da4 (diff) | |
| download | coreboot-7e703d77b2cb2189863d2a2e87f7de2913e20307.tar.gz coreboot-7e703d77b2cb2189863d2a2e87f7de2913e20307.tar.bz2 coreboot-7e703d77b2cb2189863d2a2e87f7de2913e20307.zip | |
soc/amd/cezanne/fch: add ACPI I/O port setup
The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from
the reference code, but not the PPR. I've submitted a change request for
the PPR, so this mismatch might go away in the future. The case for
HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends
up being identical to the function in soc/amd/picasso, I'll move it to
the common AMD SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/include/soc/iomap.h')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 20f70371f081..01b06479d8b7 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -16,6 +16,16 @@ /* I/O Ranges */ #define NCP_ERR 0x00f0 +#define ACPI_IO_BASE 0x0400 +#define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) +#define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) +#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) +#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) +#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) +#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) +#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) +#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) #define SMB_BASE_ADDR 0x0b00 #endif /* AMD_CEZANNE_IOMAP_H */ |