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| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2021-10-12 23:35:11 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-15 19:18:26 +0000 |
| commit | c2cee06b4efb8992e625ca4554df17c7ef457930 (patch) | |
| tree | c492e9020bb353dc51e94b5dc1d1f062a6ca66d9 /src/soc/amd/cezanne/include/soc/iomap.h | |
| parent | 6c08b1ff8180181ff50150a17ae94abde9ffc2f2 (diff) | |
| download | coreboot-c2cee06b4efb8992e625ca4554df17c7ef457930.tar.gz coreboot-c2cee06b4efb8992e625ca4554df17c7ef457930.tar.bz2 coreboot-c2cee06b4efb8992e625ca4554df17c7ef457930.zip | |
soc/amd/common/block/i2c: implement proper read_resource
Before this patch the reservation of the MMIO region of the I2C
controllers was done in the LPC controller PCI device despite the I2C
controllers already being devices in the devicetree. This patch
implements this functionality as read_resources function of the I2C
device instead. This will only reserve the memory when the I2C devices
are enabled in devicetree which is a change from the previous behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/include/soc/iomap.h')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 236578b94545..a4f0f30d8041 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -28,11 +28,6 @@ #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 -/* I2C parameters for lpc_read_resources */ -#define I2C_BASE_ADDRESS APU_I2C2_BASE -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT (I2C_MASTER_DEV_COUNT - I2C_MASTER_START_INDEX) - #define APU_DMAC0_BASE 0xfedc7000 #define APU_DMAC1_BASE 0xfedc8000 #define APU_UART0_BASE 0xfedc9000 |