diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-09 23:04:29 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-13 22:18:03 +0000 |
| commit | dffdea8a76e6ebc0f94ad25083983ae538f1d077 (patch) | |
| tree | 6367e57fbe58a2f94c309fd48ad511ed7b465435 /src/soc/amd/cezanne/include/soc/iomap.h | |
| parent | 7584e550ccba903903be6603f50dc8519a382564 (diff) | |
| download | coreboot-dffdea8a76e6ebc0f94ad25083983ae538f1d077.tar.gz coreboot-dffdea8a76e6ebc0f94ad25083983ae538f1d077.tar.bz2 coreboot-dffdea8a76e6ebc0f94ad25083983ae538f1d077.zip | |
soc/amd/cezanne: add caching setup in bootblock
The code can likely be factored out to common code, but since I'm not
entirely sure yet that there will be no differences, I'll copy for now
instead.
Change-Id: I5fc158518cf9534ab9727f3305abeb4b34049e76
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/include/soc/iomap.h')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/iomap.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 4d47f7ed57b2..b377ee31fb5e 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -3,6 +3,9 @@ #ifndef AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H +/* MMIO Ranges */ +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define NCP_ERR 0x00f0 #define SMB_BASE_ADDR 0x0b00 |